The engineering evidence behind ACIX.

Engineering record

Six systems, and what each one demonstrates.

Each entry below is work already built and run on hardware. Where the work was carried out under confidentiality, the architecture and interfaces are described and the parties are not.

1. 01

   Structural-health-monitoring system

   Carried out in previous employment, for a separate industrial partner. Neither party can be named under confidentiality.

   Integration of an existing data-acquisition platform with acoustic modems for underwater communication, extending the system for a more complex field deployment.

   Embedded firmware

   STM32 control firmware covering power management, shutdown and wake-up sequencing, and the system’s state machine. An acoustic modem control layer and transmission API, and a custom SPI link between an embedded-Linux modem and the FPGA.

   Integration and handover

   Ownership of the digital backend across the FPGA, embedded-Linux and microcontroller boundaries, with additional control states added for the integrated system, and client-facing and internal documentation produced alongside it.

2. 02

   Zynq SoC acquisition platform

   Carried out in previous employment.

   A Zynq SoC acquisition platform built from scratch: RTL architecture, AXI4-Stream, AXI-Lite and AXI-DMA data paths, processing-system integration and PetaLinux bring-up, with Ethernet communication to a host PC. Migrating the transfer path from external SPI to AXI-DMA inside the SoC removed external points of failure and moved transfer latency from milliseconds to microseconds.

   ms → µs transfer latency, SPI→AXI-DMA migration
3. 03

   Acceleration and optimisation in fabric

   Carried out in previous employment.

   Operations moved out of software into FPGA fabric, or re-architected for throughput, on an existing platform.

   Kinematics in fabric

   Encoder kinematics computation pipelines implemented on the FPGA rather than in software.

   Channel encoding

   Communication channels re-encoded from fixed-point to 16-bit float, removing the need for an additional 8-bit SPI transfer and reducing combined transfer-and-processing time by roughly a third.

   Clocking and monitoring

   A dynamically reconfigurable clock, with XADC and Dynamic Reconfiguration Port integration on Xilinx devices.

   ~33% transfer-plus-processing reduction, fixed→float16
4. 04

   High-voltage analogue front-end

   Internal research and development, in previous employment.

   High-voltage pulsed EMAT drive hardware, developed and laboratory-validated for the NDT/industrial-inspection application.

5. 05

   Signal-processing pipeline

   Independent research into an FMCW LiDAR acquisition and processing chain, taken as far as a working signal path in fabric and verified against a reference model.

   Acquisition and processing

   An acquisition chain of ADC capture → NCO → mixer → FIR decimation ×32 → FFT, with PetaLinux bring-up and Python tooling, and on-chip debug via ILA and Tcl automation.

   Verification

   Fixed-point conversion checked bit-accurately against a MATLAB reference model across roughly 1,000 Monte Carlo runs with zero divergence, alongside corner-case and reset testing.

   ~1,000 runs Monte Carlo verification, zero divergence
6. 06

   Signal generator, Cyclone V SoC

   Independent project.

   A signal generator built on an Altera Cyclone V SoC with an ARM Cortex-A9 hard processor system: a purpose-built analogue front end, a parallel signalling interface implemented in both analogue hardware and FPGA fabric for processing, and signal generation driven from Linux running on the ARM core.

Published research

MEng thesis, Imperial College London.

Completed 2026. Power hardware-in-the-loop interfaces — specifically DAC/ADC delay compensation and H∞ synthesis for stabilising active inverter systems. Published by Imperial College London under a Creative Commons licence.

Demonstrated competences

What the work above evidences.

• FPGA / RTL

  VHDL, Verilog and SystemVerilog; RTL architecture from scratch; FSMs; control/datapath separation; pipelining; fixed-point arithmetic; parameterised, streaming architectures; hardware–software partitioning.

• Platforms and toolflow

  AMD/Xilinx Zynq-7000, Zynq UltraScale+, ZCU104 and Artix-7; Intel/Altera Cyclone V on an independent project; Vivado, Vitis and PetaLinux; ModelSim/QuestaSim; synthesis, place-and-route, static timing analysis and timing closure.

• Interfaces and clocking

  AXI4, AXI4-Stream, AXI-Lite and AXI DMA; SPI, UART, I²C and Ethernet integration; clock-domain crossing and reset-domain design; metastability-aware, multi-clock systems.

• Embedded software

  Embedded Linux and PetaLinux build/deploy; bare-metal firmware; STM32; power-state control and shutdown/wake sequencing; Python hardware-control APIs.

• Analogue and instrumentation

  Low-noise amplification; active and passive filtering; mains-rejection design; high-voltage pulsed drive hardware; LTspice/SPICE modelling; grounding, shielding and signal integrity.

• PCB and lab

  Schematic capture and PCB design in KiCad, with Altium exposure; PCBA bring-up and SMD rework; oscilloscopes, logic analysers, spectrum and network analysers, function generators and bench supplies.

• Languages and tooling

  Python, C, C++, MATLAB, Simulink, Tcl and Bash; Git, GitHub and GitHub Actions; PyTest.

  Exposure only: C++ depth, ROS2, RTOS, formal verification